module PORTICUS(
/*----------------------MainClk----------------------*/
	input			ClkIn50M,		//50M

/*----------------------Sampling Ch0----------------------*/
//DataFromDBoard
	input	[15:0]	CH0_DATA,
	input			CH0_DATA_CLK,
	output			CH0_DATA_CS,

//DBoardClk
	output			CH0_IOCLK,

//InformationExch
	output			CH0_MUT_CLK,
	output			CH0_MUT_CS,
	input			CH0_MUT_MISO,
	output			CH0_MUT_MOSI,


//TypeNum
	output	[3:0]	CH0_SEQ,

//trigger
	output			CH0_TR_IN,
	input			CH0_TR_OUT,

/*----------------------Sampling Ch1----------------------*/
//DataFromDBoard
	input	[15:0]	CH1_DATA,
	input			CH1_DATA_CLK,
	output			CH1_DATA_CS,

//DBoardClk
	output			CH1_IOCLK,

//InformationExch
	output			CH1_MUT_CLK,
	output			CH1_MUT_CS,
	input			CH1_MUT_MISO,
	output			CH1_MUT_MOSI,

//TypeNum
	output	[3:0]	CH1_SEQ,

//trigger
	output			CH1_TR_IN,
	input			CH1_TR_OUT,

/*----------------------Sampling Ch2----------------------*/
//DataFromDBoard
	input	[15:0]	CH2_DATA,
	input			CH2_DATA_CLK,
	output			CH2_DATA_CS,

//DBoardClk
	output			CH2_IOCLK,

//InformationExch
	output			CH2_MUT_CLK,
	output			CH2_MUT_CS,
	input			CH2_MUT_MISO,
	output			CH2_MUT_MOSI,

//TypeNum
	output	[3:0]	CH2_SEQ,

//trigger
	output			CH2_TR_IN,
	input			CH2_TR_OUT,

/*----------------------Sampling Ch3----------------------*/
//DataFromDBoard
	input	[15:0]	CH3_DATA,
	input			CH3_DATA_CLK,
	output			CH3_DATA_CS,

//DBoardClk
	output			CH3_IOCLK,

//InformationExch
	output			CH3_MUT_CLK,
	output			CH3_MUT_CS,
	input			CH3_MUT_MISO,
	output			CH3_MUT_MOSI,

//TypeNum
	output	[3:0]	CH3_SEQ,

//trigger
	output			CH3_TR_IN,
	input			CH3_TR_OUT,

/*----------------------PCIE Interface----------------------*/
//PCIE Interface
	input			ADSN,		//总线使能
	input			LHOLD,	//请求
	input			LWRN,		//读写使能
	input			BLASTN,	//同步
	input			LREST,	//复位
	input	[31:0]	LA,		//PCIE地址
	inout	[31:0]	PXI_LD,	//PCIE数据
	output			READYN,	//数据有效
	output			LHOLDA,	//请求回应

/*----------------------TRIGGER----------------------*/
	input			TRIGGERINF,
	output			TRIGGEROUTF,
	input			CLKINF,
	output			CLKOUTF,

/*----------------------Digital Channel----------------------*/
	output	[19:0]	DIGIO,			//TestIO
	input	[19:0]	DIGION			//TestIO
);


assign CH0_SEQ[0] = TRIGGERINF;
assign CH1_SEQ[0] = TRIGGERINF;
assign CH2_SEQ[0] = TRIGGERINF;
assign CH3_SEQ[0] = TRIGGERINF;
/*----------------------Digital Channel----------------------*/
wire[15:0] DIGOUT;
wire[1:0] DIGIN;
assign {DIGIO[16],DIGIO[10],DIGIO[2],DIGIO[9],DIGIO[1],DIGIO[11],DIGIO[15],DIGIO[7],DIGIO[12],DIGIO[14],DIGIO[0],DIGIO[8],DIGIO[13],DIGIO[6],DIGIO[4],DIGIO[19]} = DIGOUT;
assign DIGIN = {DIGION[17],DIGION[5]};
assign TRIGGEROUTF = CH0_TR_IN;
assign CLKOUTF = clk10M;
/*----------------------PLL----------------------*/
wire Clk;
wire clk100M;
wire clk10M;
wire clk200M;
wire plllock;
PLLC Upll(
	.inclk0(ClkIn50M),

	.c0(Clk),
	.c1(clk100M),
	.c2(clk10M),
	.c3(clk200M),

	.locked(plllock)
);

wire clkselect;
assign CH0_IOCLK = clkselect ? CLKINF : clk10M;
assign CH1_IOCLK = clkselect ? CLKINF : clk10M;
assign CH2_IOCLK = clkselect ? CLKINF : clk10M;
assign CH3_IOCLK = clkselect ? CLKINF : clk10M;

/*----------------------SystemRst----------------------*/
wire rst_n;		//先低后高，上升沿
sys_rst USysRst(
	.clk(ClkIn50M),
	.systemclk_locked(plllock),

	.rst_n(rst_n)
);

/**/
//assign DIGIO[0] = clk100M;
/**/

/*----------------------PcieToComputer----------------------*/
wire enWr,enRd;
wire[31:0] pciWrData/* synthesis keep */;
wire[31:0] pciAddr/* synthesis keep */;
wire[31:0] READ_DATA;
// assign PXI_LD = (READYN) ? 32'bz : READ_DATA;
// pcie8311 UPCIe(
// 	.clk(ClkIn50M),
// 	.ads_n(ADSN),
// 	.blast_n(BLASTN),
// 	.la({16'h0,LA[31:30],LA[13:2]}),			//[31:2]
// 	.lhold(LHOLD),
// 	.lholda(LHOLDA),
// 	.lwr_n(LWRN),
// 	.PXI_LD(PXI_LD),		//[31:0]
// 	.ready_n(READYN),

// 	.data_valid(1'b1),	//上位机读数据准备完成

// 	.data_latch(pciWrData),	//[31:0]上位机写数据
// 	.addr_en(),
// 	.wren(enWr),	//1有效
// 	.rden(enRd),	//1有效
// 	.addr(pciAddr),			//[31:0]上位机地址
// 	.pcie_busy(),
// 	.response_finish()
// );

DMA8311 UDMA(
	.clk(ClkIn50M),
	.rst_n(rst_n),
	.ads_n(ADSN),
	.blast_n(BLASTN),
	.la({16'h0,LA[31:30],LA[13:2]}),
	.lhold(LHOLD),
	.lwr_n(LWRN),
	.PXI_LD(PXI_LD),
	.lholda(LHOLDA),
	.ready_n(READYN),

	.data_latch(pciWrData),
	.addr(pciAddr),
	.READ_DATA(READ_DATA)
);


reg[31:0] wrAddr,wrData;


decoder UdeCode(
	.clk_in(Clk),
	.rst_n(rst_n),

	.Addr(pciAddr),
	.RdData(READ_DATA),
	.WrData(pciWrData),

/*----------CH0--------------------------------*/
	.CH0_addr(CH3_addr),
	.CH0_data_w(CH3_data_w),
	.CH0_data_r(CH3_data_r),

/*----------CH1--------------------------------*/
	.CH1_addr(CH0_addr),
	.CH1_data_w(CH0_data_w),
	.CH1_data_r(CH0_data_r),

/*----------CH2--------------------------------*/
	.CH2_addr(CH1_addr),
	.CH2_data_w(CH1_data_w),
	.CH2_data_r(CH1_data_r),

/*----------CH3--------------------------------*/
	.CH3_addr(CH2_addr),
	.CH3_data_w(CH2_data_w),
	.CH3_data_r(CH2_data_r),

/*----------DIG--------------------------------*/
	.dataIn_code(dataIn_code),
	.wr_addr_code(wr_addr_code),
	.wr_en_code(wr_en_code),
	.data_range(data_range),
	.pulse_range(pulse_range),
	.max_addr(max_addr),
	.code_rst_n(code_rst_n),
	.dioin(dioin),
	.dinaclr(dinaclr),
	.rd_code(rd_code),
	.DIO_IN(DIO_IN),
	.clkselect(clkselect),
	
	.VerusTrigger(VerusTrigger),
	.TriggerMode(TriggerMode),
	.VT_st(VT_st),
	.VT_gt(VT_gt),
	.TriggerDNum(TriggerDNum),


	.test_port()

);

wire[15:0] CH0_addr;
wire[31:0] CH0_data_w;
wire[31:0] CH0_data_r;
MutMS UMutMS0(
	.clk100M(clk100M),
	.rst_n(rst_n),
	.addr(CH0_addr),		//底板到子板写地址
	.data_w(CH0_data_w),		//底板到子板写数据
	.data_r(CH0_data_r),		//底板到子板读数据

	.spi_cs	(CH0_MUT_CS),
	.spi_clk(CH0_MUT_CLK),
	.spi_miso(CH0_MUT_MISO),
	.spi_mosi(CH0_MUT_MOSI)
);

wire[15:0] CH1_addr;
wire[31:0] CH1_data_w;
wire[31:0] CH1_data_r;
MutMS UMutMS1(
	.clk100M(clk100M),
	.rst_n(rst_n),
	.addr(CH1_addr),		//底板到子板写地址
	.data_w(CH1_data_w),		//底板到子板写数据
	.data_r(CH1_data_r),		//底板到子板读数据

	.spi_cs	(CH1_MUT_CS),
	.spi_clk(CH1_MUT_CLK),
	.spi_miso(CH1_MUT_MISO),
	.spi_mosi(CH1_MUT_MOSI)
);

wire[15:0] CH2_addr;
wire[31:0] CH2_data_w;
wire[31:0] CH2_data_r;
MutMS UMutMS2(
	.clk100M(clk100M),
	.rst_n(rst_n),
	.addr(CH2_addr),		//底板到子板写地址
	.data_w(CH2_data_w),		//底板到子板写数据
	.data_r(CH2_data_r),		//底板到子板读数据

	.spi_cs	(CH2_MUT_CS),
	.spi_clk(CH2_MUT_CLK),
	.spi_miso(CH2_MUT_MISO),
	.spi_mosi(CH2_MUT_MOSI)
);

wire[15:0] CH3_addr;
wire[31:0] CH3_data_w;
wire[31:0] CH3_data_r;
MutMS UMutMS3(
	.clk100M(clk100M),
	.rst_n(rst_n),
	.addr(CH3_addr),		//底板到子板写地址
	.data_w(CH3_data_w),		//底板到子板写数据
	.data_r(CH3_data_r),		//底板到子板读数据

	.spi_cs	(CH3_MUT_CS),
	.spi_clk(CH3_MUT_CLK),
	.spi_miso(CH3_MUT_MISO),
	.spi_mosi(CH3_MUT_MOSI)
);

wire[15:0] dataIn_code;
wire[9:0] wr_addr_code,max_addr;
wire[31:0] data_range,pulse_range;
wire[13:0] dioin;
wire[1:0] DIO_IN;
wire rd_code;
wire wr_en_code;
wire code_rst_n;
wire dinaclr;
CodePattern Ucode(
	.clk100M(clk100M),
	.clk200M(clk200M),
	.rst_n(code_rst_n),
	.dataIn(dataIn_code),
	.wr_addr(wr_addr_code),
	.wr_en(wr_en_code),
	.max_addr(max_addr),
	.dioin(dioin),
	.rd_code(rd_code),
	.DIO_IN(DIO_IN),
	.dinaclr(dinaclr),
	
	.data_range(data_range),
	.pulse_range(pulse_range),
	
	.PatternIn(DIGIN),
	.PatternOut(DIGOUT)
);

wire VT_st;
wire VT_gt;
wire VerusTrigger;
wire[1:0] TriggerMode;
wire[3:0] TriggerDNum;
MTrigger UTR(
    .clk50M(Clk),
    .rst_n(VT_gt),
    .TriggerMode(TriggerMode),
    .VT_st(VT_st),
	.TriggerDNum(TriggerDNum),

    .CH0_TR_OUT(CH3_TR_OUT),
    .CH0_TR_IN(CH3_TR_IN),
    .CH0_DRange_gt(CH3_DATA_CLK),
    .CH0_TriggerST(CH3_DATA_CS),

    .CH1_TR_OUT(CH0_TR_OUT),
    .CH1_TR_IN(CH0_TR_IN),
    .CH1_DRange_gt(CH0_DATA_CLK),
    .CH1_TriggerST(CH0_DATA_CS),

    .CH2_TR_OUT(CH1_TR_OUT),
    .CH2_TR_IN(CH1_TR_IN),
    .CH2_DRange_gt(CH1_DATA_CLK),
    .CH2_TriggerST(CH1_DATA_CS),

    .CH3_TR_OUT(CH2_TR_OUT),
    .CH3_TR_IN(CH2_TR_IN),
    .CH3_DRange_gt(CH2_DATA_CLK),
    .CH3_TriggerST(CH2_DATA_CS),

    .LAN(VerusTrigger),
	.TRIGGERINF(TRIGGERINF)
);

// assign CH0_TR_IN = CH2_TR_OUT;
// assign CH1_TR_IN = CH2_TR_OUT;
// assign CH2_TR_IN = CH2_TR_OUT;
// assign CH3_TR_IN = CH2_TR_OUT;

//DataMiso UMDData3(
//	.clk(Clk),			//50M时钟
//	.rst(rst_n),
//	.rd_en(),
//	.CS(),
//	.SPI_SCLK(),
//	.SPI_SDI(),
//	.SPI_SDO(),
//
//	.CMD(),			//命令
//	.STX(),			//帧头
//	.XC(),			//数据长度
//	.REC_DATA(),	//数据
//	.addr_ROM(),	//存数地址
//	.VS(),			//校验和
//	.ETX()			//帧尾
//);

endmodule
